Bonding pad arrangement method for semiconductor devices

ABSTRACT

A variety of pad arrangements are provided for semiconductor devices for reducing the likelihood of bonding failures, particularly those due to shorts, and/or for reducing the difference in length between bonding wires to decrease signal skew during operation of the semiconductor device and improve signal integrity.

This is a divisional application of U.S. patent application Ser. No.10/465,554, filed on Jun. 20, 2003, which claims priority under 35U.S.C. § 119 of Korean Patent Application 2002-35925 filed on Jun. 26,2002, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and, moreparticularly, to pad arrangements for reducing bonding failures andsignal skew.

2. Discussion of the Related Art

As semiconductor manufacturing processes have improved, design ruleshave been reduced to allow for smaller and/or higher densitysemiconductor devices. However, for semiconductor devices having a largenumber of pads, the pad pitch limit, or pad-to-pad design rule, maydefine the minimum size.

FIGS. 1A to 1C are views of representative pad arrangements that areused on conventional semiconductor devices. FIG. 1A illustrates pads 98arranged in a single row on a chip 100, FIG. 1B illustrates pads 98arranged in two rows on a chip 100 and FIG. 1C illustrates pads 98arranged around the periphery of a chip 100.

FIG. 2 illustrates a conventional configuration of bonding wires 104used to connect two rows of bond pads to the corresponding portions of alead frame 102. As reflected in FIG. 2, the separation between thebonding wires 104 used to connect pads 1-3, 6-11 and 14-16 to thecorresponding portions of the lead frame 102 is reduced, increasing thelikelihood that one or more shorts may be formed between a bond wire anda pad and/or an adjacent bond wire. Increasing the number of bond padstends to reduce the spacing between adjacent bond wires and to increasethe likelihood of shorts.

Further, bonding wires 104 connected between the more distant portionsof the lead frame 102 and certain of the pads, e.g., pads 1, 8, 9 and16, are substantially longer than those bonding wires connected betweencloser portions of the lead frame and other pads, e.g., pads 4, 5, 12and 13. Different bonding wire lengths may result in a timing skewbetween the signals being transmitted through the bonding wires to therespective pads. These timing skews will tend to compromise signalintegrity, disrupt high-speed operations and limit the rate at which thesemiconductor device may be successfully operated.

SUMMARY OF THE INVENTION

Accordingly, exemplary embodiments of the invention are directed to amethod of arranging pads on a semiconductor device in a manner that willtend to reduce the likelihood of shorts and/or reduce the signal timeskew during operation of the semiconductor device.

Exemplary embodiments of the invention are directed to methods ofarranging pads on semiconductor devices to allow a plurality of bondingwires to have substantially the same length.

Exemplary embodiments of the invention provide methods of arrangingpads, such as pad-on-cell (POC) type pads, on semiconductor devices toform pad groupings having an oblique arrangement with respect to thechip edge and/or other pad groupings. Exemplary pad groupingsconfigurations may be symmetrical or asymmetrical with respect to thechip edge and may include one or more V-shaped, sawtooth or zigzag-typepad arrangements that may allow reductions in the semiconductor packagesize, reduce the length variation in the bond wires, and reduce thelikelihood of shorting between bonding wires and/or pads.

It is to be understood that both the foregoing general description andthe following detailed description of the present invention areexemplary and explanatory and are intended to provide furtherexplanation to those of skill in the art of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the invention may be further understood throughthe written description and the accompanying FIGURES in which:

FIGS. 1A to 1C are plan views illustrating certain conventional padarrangements;

FIG. 2 is a view illustrating a bonding wire configuration between aconventional lead from and semiconductor device pads with an increasedlikelihood of shorting or bonding failures;

FIG. 3 is a plan view showing a pad arrangement in which lead frames arebonded with pads in accordance with a first exemplary embodiment of theinvention;

FIG. 4 is a plan view showing a pad arrangement in which lead frames arebonded with pads in accordance with a second exemplary embodiment of theinvention;

FIG. 5 is a plan view of a pad arrangement in accordance with a thirdexemplary embodiment of the invention;

FIGS. 6A and 6B are plan views of pad arrangements in accordance with afourth exemplary embodiment of the invention;

FIG. 7A is a plan view of a pad arrangement in accordance with a fifthexemplary embodiment of the invention, FIG. 7B is a plan view of a padarrangement in which the angles α and β are substantially equal, FIG. 7Cis a plan view of a pad arrangement in which the bonding wire havesubstantially equal lengths;

FIG. 8 is a plan view of a pad arrangement in accordance with a sixthexemplary embodiment of the invention;

FIG. 9 is a plan view of a pad arrangement in accordance with a seventhexemplary embodiment of the present invention; and FIG. 10 is a planview of an embodiment in which two series of pads are arranged with thecorresponding axes being substantially parallel.

DETAILED DESCRIPTION OF THE INVENTION

Exemplary embodiments of the invention will be described below withreference to accompanying drawings. This invention may, however, beembodied in many different forms and should not be construed as beinglimited to the exemplary embodiments set forth herein; rather, theseexemplary embodiments are provided so that this disclosure is thoroughand complete, and conveys the concept of the invention to those skilledin the art. In the drawings, the sizing and spacing of elements may beenlarged or reduced for clarity and are not intended to be to scale.

FIG. 3 is a plan view showing an arrangement of pads 1-16 on asemiconductor chip 100 according to a first exemplary embodiment of theinvention with portions of a conventional lead frame 102 being connectedto the pads with bonding wires 104. As illustrated in FIG. 3, pads 1-8and 9-12 are arranged to form two shallow “V” shapes having legsarranged obliquely with respect to one of the edges 106 of chip 100.

As illustrated in FIG. 3, this arrangement of the pads allows thebonding wires 104 between the several end pads on each leg of the “V”shape, i.e., pads 1-3, 6-8, 9-11 and 14-16 to be bonded to aconventional lead frame 102 while improving the separation betweenadjacent bonding wires and the overlap of other pads to reduce thelikelihood of shorting. Increasing the oblique angle between a group ofpads and the edge of the chip can increase the number of pads that maybe successfully bonded to the lead frame and permit the mounting ofsemiconductor devices having an increased number of pads.

FIG. 4 is a plan view showing an arrangement of pads 1-10 on asemiconductor chip 100 according to a second exemplary embodiment of theinvention with portions of a conventional lead frame 102 being connectedto the pads with bonding wires 104. As illustrated in FIG. 4, pads 1-5and 6-10 are arranged in opposing “V” shapes configured to allowconnection to a conventional lead frame 102 using bonding wires 104 ofsubstantially equal length. By allowing the use of bonding wires ofsubstantially equal length, this pad arrangement reduces signal skew andimproves signal integrity.

FIG. 5 is a plan view of a pad arrangement in accordance with a thirdexemplary embodiment of the invention. As illustrated in FIG. 5, aplurality of memory cell array blocks, including memory cell arrayblocks MCB0 to MCB3, and sense amplifiers, including S/A0 to S/A3, areprovided on a semiconductor chip 100. Each of the memory cell arrayblocks is associated with a pair of pads, including pads 1-10, which maybe POC-type pads. The pads in each memory cell array block are offset insuch a manner that the first pads in each of the memory cell arrayblocks are arranged in a first line and the second pads in each of thememory cell array blocks are arranged in a second line, the first andsecond lines being substantially parallel to each other and to the edge106 of the chip 100. The offset between the pads and the step distancebetween adjacent memory cell array blocks may be such that a line from afirst pad to a second pad to the next first pad, e.g., from pad 1 to pad2 to pad 3, etc., will have a somewhat zigzag or sawtooth pattern.Offsetting the pads in each of the memory cell array blocks in thismanner increases the number of pads that can be successfully bonded to alead frame when compared with pads arranged in a single row.

FIGS. 6A and 6B are plan views of pad arrangements in accordance with afourth exemplary embodiment of the present invention. As illustrated inFIG. 6A, pads 1-10, which may be POC-type pads, are arranged on asemiconductor chip 100 over a plurality of memory cell array blocks,MCB0 to MCB4, in a general “V” shape with the point of the “V” directedtoward the center of the chip. As did the pad arrangement illustrated inFIG. 4, the V-shaped pad arrangement illustrated in FIG. 6A allows thelengths of the bonding wires 104 used to connect the pads 98 and a leadframe (not shown) to be substantially equal, reducing the incidence ofsignal skew and improving the signal integrity.

As illustrated in FIG. 6B, the pads may also be arranged in a “V” shapein which the point of the “V” is directed away from the center towardthe edge 106 of the chip 100. As it did in the exemplary embodimentillustrated in FIG. 3, this pad arrangement improves the separationbetween adjacent bonding wires, particularly for those pads at the endsof the legs of the “V,” and will reduce the likelihood of shorting.

FIG. 7 is a plan view of a pad arrangement in accordance with a fifthexemplary embodiment of the present invention. As illustrated in FIG. 7,pads 1-10 are again arranged to form a somewhat asymmetric “V” shape.Pads 1-5 are generally aligned along a first line 108 defining a firstoblique angle a with the edge 106 of chip 100. Similarly, pads 6-10 aregenerally aligned along a second line 110 defining a second obliqueangle β with the edge 106 of chip 100. The selection of different anglesα and β allows the pad arrangement to be adjusted to compensate for theoff-center mounting of the chip 100 within a lead frame (not shown). Inoff-center mounting configurations, such as may be used in a multi-chippackage, the selection of the angles α and β chips can improve thebonding performance by providing a larger effective angle for pads thatare to be bonded to more distant portions of the lead frame whileproviding an angle that will tend to equalize the lengths of the bondingwires to pads that will be connected to closer portions of the leadframe.

FIG. 8 is a plan view of a pad arrangement in accordance with a sixthexemplary embodiment of the present invention. As illustrated in FIG. 8,pads 1 to 10 are arranged over memory cell array blocks MCB0 to MCB4 inan asymmetric “V” shape with pads 1-5 forming a first leg of the “V” andpads 6-10 forming the second leg. Like the pad arrangement illustratedin FIG. 7, the oblique angle α formed between a line 108 though pads 1to 5 and the edge 106 of chip 100 is different than the angle β formedbetween a line 110 through pads 6-10 and the edge 106 of chip 100.

FIG. 9 is a plan view of a pad arrangement in accordance with a seventhexemplary embodiment of the present invention. The pad arrangementillustrated in FIG. 9 is substantially similar to the pad arrangementillustrated in FIG. 8, except that the pads of FIG. 9 are conventionalpads arranged on a semiconductor substrate rather than POC-type pads.The reasons for and the benefits resulting from such a pad arrangementare similar to those discussed in connection with FIG. 8.

Pad arrangements in accord with the exemplary embodiments of theinvention make it possible to reduce the occurrence of shorts betweenthe bonding wires, the pads and/or the lead frame in a semiconductorpackage. Pad arrangements in accord with the exemplary embodiments ofthe invention may also make it possible to reduce the difference in thelength of the bonding wires, thereby reducing signal skew and improvingsignal integrity.

It will be apparent to those skilled in the art that variousmodifications and variations can be made in the present invention. Thus,it is intended that the present invention covers the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

1. A semiconductor device having a plurality of bond pads comprising: aplurality of bond pad pairs, each pair of bond pads including a firstbond pad and a second bond pad, wherein each of the first bond pads ispositioned at a first perpendicular distance from a first edge of thesemiconductor device; and each of the second bond pads is positioned ata second perpendicular distance from the first edge of the semiconductordevice and separated from a corresponding first bond pad by a thirddistance in a direction parallel to the first edge of the semiconductordevice, wherein: the first and second perpendicular distances are notidentical.
 2. The semiconductor device according to claim 1, wherein:the semiconductor device is configured as a pad-on-cell (POC) deviceincluding a plurality of memory cell array blocks, and wherein at leastone bond pad pair is arranged on each memory cell array block.
 3. Thesemiconductor device according to claim 2, wherein: each second bond padis separated from an adjacent non-paired first bond pad by a stepdistance in a direction generally parallel to the first edge of thesemiconductor device.
 4. The semiconductor device according to claim 3,wherein: the third distance is an offset distance.
 5. The semiconductordevice according to claim 3, wherein: the offset distance and the stepdistance are approximately equal.
 6. The semiconductor device accordingto claim 3, wherein: a ratio between the offset distance and the stepdistance is at least 1:4.
 7. A semiconductor package comprising: asemiconductor device according to claim 1; a lead frame, the lead frameincluding a plurality of connection regions, the connection regionsbeing arranged along an axis substantially parallel to the first edge ofthe semiconductor device; and a plurality of bond wires extendingbetween connection regions of the lead frame and the bond pads, wherein:the semiconductor device is configured as a pad-on-cell (POC) devicethat includes a plurality of memory cell array blocks, and furtherwherein, at least one bond pad pair is arranged over each memory cellarray block.
 8. A semiconductor package according to claim 7, wherein:the semiconductor device includes a second edge parallel to the firstedge; third and fourth edges perpendicular to the first and secondedges; and a plurality of third bond pads arranged adjacent at least oneof the second, third and fourth edges of the semiconductor device. 9.The semiconductor package comprising: a semiconductor device accordingto claim 1, wherein the semiconductor device is configured as apad-on-cell (POC) device that includes a plurality of memory cell arrayblocks separated by a plurality of sense amplifiers and wherein adjacentones of the bond pads are arranged over at least one memory cell arrayblock.
 10. The semiconductor package according to claim 9, wherein: thebond pad pairs are positioned outside a periphery of the senseamplifiers.
 11. The semiconductor package according to claim 9, wherein:the semiconductor device includes a second edge parallel to the firstedge; third and fourth edges perpendicular to the first and secondedges; and a plurality of third bond pads arranged adjacent at least oneof the second, third and fourth edges of the semiconductor device.